LiquidMemory™
LiquidMemory consists of three component memories:
1) Multi-Port Register Files
This is the most effective means of composing small-size scratch-pad
memories. Targeted for memory instances of up to8 K, which can be
placed anywhere within our Sea of Transistors core logic section
(described in LiquidCell).
2) SRAM High-Density Memory
This flexible SRAM dual-port memory (which we compile from
single-port memories) can be compiled to support a wid range of
applications.
3) One-Time Programmable (OTP) Memory
This non-volatile memory is a component of SoC designs. It supports a variety of applications.
Features
- High-Density SRAM Memory
Utilizes foundries’ 6-T cell bit cell.
Single instances up to 8K bits.
Provided in two different configurations, 1kx36 and 8kx32 SRAM blocks.
Available in single-port & dual-port.
Fixed number of instances per slice.
Supports wider bus width and/or deeper memory configurations.
Shares key infrastructure (BIST & BISA) across all SRAM memories (enabling soft repair & package test).
Single instances up to 8K bits.
Provided in two different configurations, 1kx36 and 8kx32 SRAM blocks.
Available in single-port & dual-port.
Fixed number of instances per slice.
Supports wider bus width and/or deeper memory configurations.
Shares key infrastructure (BIST & BISA) across all SRAM memories (enabling soft repair & package test).
- Multi-Port Programmable Register File
Compiled into the Sea of Gates area.
Seamlessly integrated along with the logic blocks.
Size up to 8kB are limited only by Sea of Gates availability.
Seamlessly integrated along with the logic blocks.
Size up to 8kB are limited only by Sea of Gates availability.
- One-Time Programmable (OTP) Memory
Enables the trim and calibration of certain analog blocks required in sub-systems (such as USB2.0).
Embedded, non-volatile.
Programmed at probe or final test.
Enables the repair of the high-density memory blocks.
Enables chip-specific information (e.g. encryption keys, system information, boot code, etc.).
Embedded, non-volatile.
Programmed at probe or final test.
Enables the repair of the high-density memory blocks.
Enables chip-specific information (e.g. encryption keys, system information, boot code, etc.).
Benefits
- Operating frequency ranges from 300 - 700MHz.
- Up to 4 port: 1R/1W, 1R/2W, 2R/1W & 2R/2W.
- Model support for standard EDA tools and flows.
- Supports the following configurations:
1read 1write
1read 2write
2read 1write
2read 2write
1read 2write
2read 1write
2read 2write
- Provides efficiency and flexibility in realizing small scratch-pad memories (e.g. for a FIFO application).
- Metal configurable: Instance location anywhere within Sea of Transistor array.
- Enables repair for high-density memory blocks, trim & calibration, and chip-specific information.
Product Briefs
| Feature | Type | Product Brief | Data Sheet |
|---|---|---|---|
 |
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| Memory | SRAM, Register File, OTP |  Available Soon |
Request Info |