LiquidIP™

What sets our IP apart is its system-level approach to design. Instead of assembling ICs from a grouping of independent IPs, Rapid Bridge has developed a system of interdependent silicon-proven IPs that provides industry-leading performance with the lowest IC implementation risks. The combination of Liquid IP building blocks and an automated floor-planning tool yields a powerful design system solution can be developed in metal (only) layers to create a System on Chip (SoC) solution within industry EDA tool flows.

LiquidIO™

LiquidIO supports over 40 industry-standard interfaces with one common base IO cell. Each IO base cell is configured to one of the 40+ interface standards with a copper overlay cell, creating a truly flexible interface. LiquidIO and LiquidMXS solutions are controlled by a Central Calibration Unit that regulates voltage, current and impedances to improve signal quality and to reduce power/ground resources for ESD, Latchup and SSO.

LiquidMXS™

Mixed Signal solutions (PLLs, DLLs, Voltage Regulators, etc) share a common base footprint that can be copper-configured to 20+ mixed signal functions. LiquidMXS instances can reside in the IO Ring or the Core area.

LiquidPHY™

LiquidPHY offers complete PHY (DDR 2/3, RLDRAM2, GDDR, USB2.0, XGMII, SGMII, etc) solutions, fully contained and embedded entirely within the IO ring for effortless and lower-risk implementation. Embedding the PHY eliminates the need to fix IO & PHY placement until the late stages of design implementation phase.

LiquidCell™

LiquidCell consists of a 700+ element standard cell library, utilizing a Sea of Transistors array that is programmed with metal-only (metal 1-3) logic cells, using industry-standard EDA tools and flows.

LiquidMemory™

LiquidMemory solution is a multi-port Register File compiler targeted for memory instances up to 8Kbits. As with our LiquidCell offering, LiquidMemory Register Files are copper overlays that can be placed anywhere within the Sea of Transistor array. With proper muxing of address and data lines, memory solutions up to 32kbits are achievable.

LiquidSerDes™

LiquidSerDes is a comprehensive Serial Link solution that is register-programmable to address multiple standards and configurations. Each LiquidSerDes instance can be register-configured to PCIe, SATA, Serial RapidIO, XAUI, CEI-6, Interlaken, Infiniband or Fibre channel interface standard. LiquidSerDes is composed of a Physical Layer (PHY): SerDes, CDR, PLL, Physical Coding Sub-layer (PCS), and all the associated test features.